Introduction

with data flooding sweeping the world and computing-intensive applications booming, traditional interconnection technologies are facing unprecedented challenges. High bandwidth, low latency, energy saving and high efficiency, these increasingly stringent requirements are driving the continuous innovation of interconnection technology. PCI Express(PCIe), as a high-speed serial point-to-point interconnection standard widely used in the industry, has become an indispensable bridge between key computing devices such as CPU, GPU, FPGA and SSD. PCI-SIG continues to promote the evolution of PCIe standards, and the release of PCIe 7.0 is undoubtedly another important milestone in the development history of interconnection technology.

Main features of PCIe 7.0

• double bandwidth: the core goal of PCIe 7.0 is to increase the bandwidth to 128 GT/s compared with PCIe 6.0, it doubles and is four times that of PCIe 5.0. With x16 configuration, up to 512 GB/s the bidirectional transmission speed. This leap in bandwidth is crucial for processing massive data transmission, especially in AI and HPC fields, which can effectively mitigate data bottlenecks.
• PAM4 signal: PCIe 7.0 follows the PAM4(Pulse Amplitude Modulation with 4 levels) signal technology introduced by PCIe 6.0. PAM4 technology encodes two-digit data in each clock cycle, thus effectively improving the data transmission rate without significantly increasing the frequency.
• Low latency and high reliability: PCIe 7.0 is always committed to maintaining low latency and high reliability data transmission, which is critical for applications with extremely high real-time requirements.
• Power efficiency: while providing higher bandwidth, PCIe 7.0 also takes improving power efficiency as an important goal, and strives to reduce power consumption as much as possible while improving performance, this is essential to reduce data center operating costs and environmental impacts. Although the actual device power consumption may increase, the efficiency (ratio of transmission speed to power consumption) is expected to increase.
• Backward compatibility: PCIe 7.0 maintains backward compatibility with all previous PCIe versions, which means that old devices can be inserted into PCIe 7.0 slots and vice versa. The system will automatically negotiate and use the highest speed supported by both parties to protect user investment to the greatest extent.
• Channel parameter optimization: in order to cope with higher frequencies, PCIe 7.0 focuses on the optimization of channel parameters and transmission distance. It is necessary to carefully adjust the physical characteristics of the signal path to ensure the integrity and reliable transmission of signals.

Main objectives of PCIe 7.0

• meet the requirements of data-intensive applications: PCIe 7.0 is designed to meet the needs of 800g Ethernet, AI/ML, HPC, quantum computing, ultra-large-scale data centers, cloud and other data-intensive emerging applications.
• Solve the AI Bandwidth Challenge: as the complexity of AI models increases rapidly (doubling every 4-6 months), the demand for bandwidth also increases exponentially. PCIe 7.0 aims to provide sufficient bandwidth and low-latency interconnection for data centers to meet the needs of large-scale parallel computing such as AI training and reasoning.
• Promote the development of high-speed SSD: PCIe 7.0 is expected to promote the development of M.2 SSD, enabling it to achieve a sequential read speed of 50 Gb/s or even higher, further releasing the performance potential of storage devices.
• Accelerate Data Center interconnection: PCIe 7.0 can support high-speed data transmission within and between different data centers, especially when using optical fiber for long-distance transmission, which will significantly improve the interconnection efficiency between data centers.
• Maintain PC interconnection standards: the development of PCIe 7.0 aims to maintain PCIe as the golden standard for PC Connection, avoid fragmentation due to the adoption of proprietary interconnection standards in the market, and maintain the healthy development of the ecosystem.
• Pave the way for future technologies: the release of PCIe 7.0 also lays the foundation for future higher-speed interconnection technologies such as PCIe 8.0. PCIe 8.0 is expected to provide up to 1TB/s bandwidth.

Application fields of PCIe 7.0

PCIe 7.0, as a high-bandwidth and low-latency I/O interconnection technology, will play an important role in the following key areas:

• artificial intelligence (AI) and machine learning (ML): PCIe 7.0 provides two-way bandwidth of up to 512 Gb/s and ultra-low latency, which can fully meet the requirements of AI workloads for large-scale parallel computing and effectively alleviate data bottlenecks, it also supports multiple accelerators to work together and connect hundreds of accelerators and high-throughput I/O networks to efficiently train AI models.
• High performance computing (HPC): HPC applications have extreme requirements for data transmission speed and efficiency. The high bandwidth and low latency of PCIe 7.0 make it a key component of HPC environment, enabling efficient connection between processors, accelerators, network cards and other components, for example, in large machine learning model training, multiple GPUs are directly interconnected through PCIe 7.0, which can significantly shorten the training time.
• Data Center: PCIe 7.0 will play an important role in ultra-large data centers and cloud environments to cope with the growing demand for high-speed data transmission within and between data centers. Especially in today's increasingly popular AI applications, data centers need higher bandwidth and lower latency to process large amounts of data.
• 800g Ethernet: the high bandwidth of PCIe 7.0 can support 800g and higher Ethernet connections to meet the explosive growth of network data transmission.
• Quantum computing: PCIe 7.0 is also expected to be applied to the emerging quantum computing field, providing high-speed interconnection for various components of quantum computers.
• Other fields: PCIe 7.0 will also play an important role in military, aerospace and other data-intensive fields.

Technical details of PCIe 7.0

• physical layer: PCIe 7.0 doubles the bus frequency at the physical layer and follows the PAM4 signal modulation technology of PCIe 6.0. The development focuses on optimizing the parameters of the signal channel and the physical length of the connection to ensure that the signal can be reliably transmitted before a repeater or switch is needed. This means that higher requirements are put forward for PCB wiring, connector design and chip packaging.
• Bandwidth per channel: each PCIe 7.0 channel is expected to provide a one-way transmission speed of 16 Gb/s, and the two-way transmission speed can reach 32 Gb/s. This provides sufficient interface bandwidth for high-bandwidth devices.
• Connector: the connector design of PCIe 7.0 focuses on reducing reflection and crosstalk, ensuring low cable loss, clear conductor termination, and minimizing tilt and periodic resonance. New indicators, such as return loss, are being discussed to improve signal quality and reliability at higher speeds.
• Signal Integrity: because PCIe 7.0 has a higher frequency, it requires finer chip level, circuit board and package collaborative design to control jitter and ensure signal integrity. This requires the use of advanced simulation tools and strict testing procedures.
• Optical connection: in order to break through the limitations of copper cables in high-speed and long-distance transmission, PCI-SIG set up PCIe optical working group. Fiber-based PCIe solutions are being developed to achieve longer transmission distances, higher bandwidth, lower latency, and better heat dissipation management. These schemes include photoelectric Conversion high-Performance Controller, PHY, optical engine, and long-distance lossless transmission. Optical interconnection is considered as an important direction for PCIe development in the future.

Development of PCIe 7.0 specifications

PCI-SIG is responsible for formulating PCIe standards. The goal of the PCIe 7.0 specification is to increase the data transmission speed to 128 GT/s, which is twice that of PCIe 6.0 and four times that of PCIe 5.0. PCI-SIG plans to release a new PCIe standard every three years.

Specification Release: version 0.7 of PCIe 7.0 has been released to members for review, and the final version is expected to be officially released in 2025. Previous versions include v0.3 and v0.5. v0.7 mainly integrates members' feedback on v0.5. PCI-SIG members are actively participating in the formulation and review of norms.

Hardware time to market: although the specification is expected to be completed in 2025, the actual PCIe 7.0 hardware, such as Motherboard and SSD, may take several years to go public, and is expected to be around 2027 or 2028. This is mainly because it takes time to develop chips and hardware, and the new PCIe standard needs to be tested and verified. Currently, PCIe 5.0 is still popular, and PCIe 6.0 devices have not been widely used.

Challenges faced by PCIe 7.0

• heat dissipation: PCIe 7.0 significantly improves data transmission speed and bandwidth, but also leads to higher operating temperatures. In order to deal with this problem, more powerful heat dissipation solutions may be needed, such as large radiators and active cooling systems. For example, Intel is developing a PCIe cooling driver for Linux, which can reduce SSD bandwidth when the temperature is too high to control the temperature.
• Cost issues: implementing PCIe 7.0 technology may increase the cost of motherboards and other components. Due to the need for more complex circuits and materials to achieve higher speed and bandwidth, this may lead to higher hardware prices for consumers in the short term.
• Practical application: although PCIe 7.0 provides huge bandwidth potential (up to 512 GB/s), many current consumer applications may not be able to fully utilize this bandwidth. For example, even for high-end game graphics cards, it is difficult to saturate the bandwidth of PCIe 5.0 at present, so the advantages of PCIe 7.0 may not be obvious in the consumer market. Therefore, PCIe 7.0 may first be applied in areas requiring high-speed data transmission, such as servers, data centers, artificial intelligence, and high-performance computing.
• Connectivity issues: from the release of new specifications to the launch of actual products, it takes time to test and verify to ensure interoperability between different devices. Even if the PCIe 7.0 specification is released in 2025, it may take several years for related hardware products to enter the market. PCIe 6.0 Standard was completed in January 2022, but interoperability testing and verification were still underway in December 2023, which indicates the complexity of the implementation of the new standard and the required verification time.
• Signal integrity: PCIe 7.0 uses PAM4 signals. In order to reach a speed of 128 GT/s, the communication frequency must be increased. Therefore, the parameters of the signal path and the physical connection length must be optimized to ensure reliable signal transmission, this brings new challenges to design and manufacturing. In order to minimize insertion loss and reflection, in the root composite reference package, it is necessary to improve connector insertion loss, return loss, PCB loss and through-hole insertion and return loss.
• Channel range: although the channel range target of PCIe 7.0 is the same as that of PCIe 6.0, in a single-connection topology, the system wiring is 4 inches to 14 inches, and AIC wiring is 2 inches to 4 inches, and the channel loss of pad-to-pad is as high as-36dB, but with the increase of speed, the challenge of signal integrity becomes more complicated.
• Challenges of optical conversion: with the increasing demand for bandwidth, the industry has begun to explore the application of PCIe protocol, the so-called "PCIe over Optics" technology, on optical links. This technology converts PCIe signals into optical signals for transmission, and utilizes the large capacity, low loss and long distance transmission characteristics of optical fibers to break through the bottleneck of distance and speed of traditional copper wire interfaces. Solutions to achieve PCIe over Optics include electro-optical conversion, high-performance controllers and PHY, optical engines, long-distance lossless transmission, modularization and standardization. In these solutions, it is necessary to solve how to maintain signal integrity, ensure the accuracy and effectiveness of optical signals converted into electrical signals, and how to realize modularization for system integration.

Conclusion

the launch of PCIe 7.0 is a major leap in data transmission technology and a forward-looking layout for future computing requirements. By significantly improving bandwidth, reducing latency, and improving energy efficiency, it has laid a solid foundation for the development of key areas such as AI, HPC, and data centers.

Although it may take longer for the consumer market to popularize PCIe 7.0, there is no doubt about its application prospect in servers, data centers and other fields. With the development of optical fiber interconnection and other technologies, PCIe 7.0 is expected to break the limitations of traditional copper cables and push computing and interconnection technologies to a new height. At the same time, it also ensures the continuous development of PCIe interconnection standards, avoids market fragmentation, and lays a foundation for future higher-speed interconnection technologies.

In the future, with the continuous improvement of PCIe 7.0 ecosystem and the gradual reduction of costs, it will bring more powerful and efficient computing experience to all walks of life. We expect PCIe 7.0 to shine brilliantly in future applications and inject new vitality into technological innovation.

The above article is forwarded from andy730